1. Field of the Invention
This invention relates to data processing.
2. Description of the Prior Art
The present invention is applicable to pipelined data processing and non-pipelined data processing. Technical background will be described with respect to a pipelined system merely to indicate a problem to be addressed.
So-called “pipelined” data processing is known, in which the operations required to handle a data processing instruction are carried out over two or more successive instruction-handling cycles (e.g. processor clock cycles).
For example, in a pipelined data processor, an instruction might be “fetched” or retrieved from memory during a first cycle under the control of a “program counter”, “decoded” during the next cycle in order to determine the meaning of the instruction and its operands, and then “executed” during a third cycle. This happens repeatedly so that while one instruction is at a certain stage in the pipeline, other instructions are at different stages, the aim being to keep the whole pipeline fully occupied as much as possible.
A problem can arise when it is desired to emulate such a pipeline using software running on another data processor.
In an emulation situation like this, each hardware operation of the data processor to be emulated is executed by a software subroutine on the emulating processor. The equivalent of the clock cycle period thus depends on the speed of operation of the slowest of these subroutines, which in turn depends on the number of operations that the emulating processor needs in order to carry out the emulated task.
The emulation clock speed has to be set to allow for this slowest emulation task. In a system which emulates real time operations or interacts with any external processing apparatus, the emulation clock speed has to be kept constant. That is to say, the emulation clock cannot be speeded up or slowed down to suit the current instruction being executed.
This can all have a further effect on the emulation of a pipelined processor, which is to restrict the ability to emulate the pipeline so that the fetch, decode and execute operations take place at the same time in respect of different instructions. Rather, a system is generally used in which each instruction is fetched, decoded and executed before the next is fetched and so on. This means that the execution of four instructions I1, I2, I3 and I4 would take twelve emulation clock cycles:
first emulated clock cyclefetch I1second emulated clock cycledecode I1third emulated clock cycleexecute I1fourth emulated clock cyclefetch I2fifth emulated clock cycledecode I2sixth emulated clock cycleexecute I2. . .. . .twelfth emulated clock cycleexecute I4